Integrated circuits are very complex devices that include multiple layers. Each layer may include conductive material, isolating material and/or semi-conductive materials. These various materials are arranged in patterns, usually in accordance with the expected functionality of the integrated circuit. The patterns also reflect the manufacturing process of the integrated circuits.
Contact hole production is a common step in semiconductor device manufacturing. The contact holes are typically used to make electrical connections to a semiconductor or metal layer through an overlying non-conducting (dielectric) layer, such as an oxide layer. In order to produce contact holes, a layer of photoresist is first deposited on the wafer surface. The photoresist is exposed to patterned visible or ultraviolet radiation, hardened, and developed in order to form a “mask” over the wafer, with mask patterns corresponding to contact hole locations. Then the wafer is transferred to an etch station where contact holes are formed through the dielectric layer, down to the underlying semiconductor or metallic layer. The photoresist mask is then removed, and the contact holes are filled with metal. A similar masking and etching process is used in producing trenches or vias in the wafer surface.
In order to ensure consistent device performance, various characteristics of the contact openings must be carefully controlled at various locations across the wafer surface. (In the context of the present patent application and in the claims, the term “contact openings” refers to all structures of the type described above, including contact holes, vias, and trenches.)
In some cases the contact hole does not define a proper contiguous space that ends at the underlying semiconductor or metallic layer. In other words, the contact hole can be at least partially filled by non-conductive material that can alter the resistance of the conductor that is later formed within the contact hole. The non-conductive material can also form a barrier between the conductive material filled within the defective contact hole and the underlying layer. Such a defect can cause an electronic circuit to be electrically “open” instead of being electrically “closed”. It can also result in higher impedance than expected from a contact that passes through a non-defective contact hole.
Voltage contrast techniques facilitate a determination of electrical properties of wafers and are based upon a detection of different charging conditions of different elements of an inspected sample. U.S. Pat. No. 6,627,884 of McCord, et al. titled “Simultaneous flooding and inspection for charge control in an electron beam inspection machine”, and U.S. Pat. No. 6,586,736 of McCord titled “Scanning electron beam microscope having an electrode for controlling charge build up during scanning of a sample”, which are incorporated herein by reference describe voltage contrast techniques.
Voltage contrast methods usually include a pre-charge stage that is followed by a scan and image stage. Some prior art methods use flooding guns that pre-charge a sample by scanning the sample with a normal incident charged particle beam. These techniques are suited to handle samples that include grounded underlying layers where underlying conducting layers remain discharged after the pre-charge stage while the oxide layer is charged, thus increasing the voltage contrast between open contact holes and their surrounding oxide layer.
FIG. 1 illustrates a cross section of a typical prior art SOI wafer 200. The lowest layer is a substrate 210. The substrate is usually made of silicone. An oxide layer (also referred to as BOX) 220 is manufactured above the substrate 210. The upper layer of the SOI wafer includes an inter-dielectric layer 240 through which contact holes 245 are fabricated. Trench insulators, such as oxide-made trench insulators 260 as well as silicone epilayer islands 230, 232, and 234, that are insulated from each other by trench isolators 260 are formed between the inter-dielectric layer 240 and the oxide layer 220.
Various wafers such as silicon over insulator (SOI) wafers and short loop wafers have sub surface structures that are intentionally floating. Thus, the pre-charging stage can charge both the inter-dielectric layer 240, any residual material within contact holes 245, and BOX layer 220. Thus, the efficiency of voltage techniques is greatly reduced.
There is a need to provide a system and method for an effective voltage contrast analysis.